1. Field of the Invention
The present invention relates to a semiconductor device such as a semiconductor memory device or a semiconductor memory-combined device having a pluglike contact hole or a pluglike local wire. In this case, the term xe2x80x9cpluglikexe2x80x9d indicates a state embedding a conductor in a hole or a groove communicating with an upper connected portion and a lower connected portion vertically separated from each other in a layer structure for electrically connecting the upper and lower connected portions with each other as shown in FIG. 17A.
2. Description of the Background Art
In recent years, a semiconductor device such as a DRAM (dynamic random access memory) is so increasingly refined that high overlay accuracy is required as to both of a bit line contact and a capacitor contact in a memory cell following reduction of the cell area, and hence self-aligned contacts (SAC) must be employed.
In a COB (capacitor over bit-line) structure forming the mainstream at present, a capacitor contact must be self-aligned with respect to both of a gate electrode and a bit line. However, the depth of the capacitor contact is about 1 xcexcm in general and hence it is technically difficult to form an opening for both of the gate electrode and the bit line through single SAC etching. In a current advanced device, therefore, an SAC opening is first formed through a stopper layer 8 formed by a silicon nitride film, as shown in FIG. 7. Referring to FIG. 8, a part of the stopper layer 8 covering a source/drain region 2 at the bottom of the opening is removed by anisotropic etching for forming a vertical hole communicating with a lower connected portion. Referring to FIG. 9, the vertical hole is filled up with polysilicon thereby forming a pluglike contact 9 as the so-called xe2x80x9clift contactxe2x80x9d. Then, a bit line contact 12 or a capacitor contact 16 reduced in diameter is formed to be connected onto the pluglike contact 9. FIGS. 17A to 18B show exemplary structures formed in the aforementioned manner.
Referring to FIG. 17A, the source/drain region 2 is connected with a it line 14 in a memory cell part. FIG. 17A is a sectional view, and FIG. 17B illustrates the positional relation as viewed from above. This also applies to the remaining figures subscripted with xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d respectively. FIGS. 17A and 17B show a semiconductor device including a gate oxide film 3, gate electrode side wall oxide films 5, a gate electrode 4, an LDD spacer 6, a mask oxide film 7, the stopper layer 8, the pluglike contact 9 and interlayer isolation films 10a and 10b, which are formed on a silicon substrate 50. The silicon substrate 50 includes element isolation regions 1 and the source/drain region 2. The bit line contact 12 is formed on the pluglike contact 9 through a barrier metal film 13. The bit line contact 12 extends downward from the bit line 14 formed on the interlayer isolation film 10b through the barrier metal film 13 for implementing downward electrical connection.
Referring to FIGS. 18A and 18B, the source/drain region 2 is connected with a capacitor lower electrode 18 in a capacitor part. While components located under an interlayer isolation film 10a in FIGS. 18A and 18B are similar to those shown in FIGS. 17A and 17B, an interlayer isolation film 10c and a capacitor isolation film 20 are formed on the interlayer isolation film 10a. The capacitor lower electrode 18 is formed on the interlayer isolation film 10c through a barrier metal film 13. A capacitor upper electrode 22 is formed on the capacitor lower electrode 18 through a capacitor dielectric film 21.
Thus, the contact is formed in a multi-step manner for reducing the depth of a hole formed at a time so that the capacitor contact 16 can be formed with a small diameter and a large depth.
In a most advanced DRAM, the bit line 14 shown in FIGS. 17A and 17B or FIGS. 19A and 19B is prepared from a low-resistance material such as W, in order to satisfy requirement for lowering the resistance value thereof. When the capacitor dielectric film 21 shown in FIGS. 18A and 18B is formed by a film of a material having a high dielectric constant such as Ta2O5, a metal material such as W resistant against oxidation is conceivably employed also for the capacitor lower electrode 18.
The material for the aforementioned pluglike contact 9 is prepared from polysilicon in consideration of affinity to silicon in heat treatment. The barrier metal film 13 consists of a two-layer structure of Ti and TiN with the layer of Ti closer to the silicon substrate 50. Therefore, the contact part has a film structure of W, TiN, Ti and polysilicon in descending order. In this case, reaction of forming TiSi takes place on the Ti/polysilicon interface in the wafer process, to increase contact resistance by excess reaction depending on heat treatment conditions. In this structure, it is difficult to attain stable low contact resistance.
Accordingly, an object of the present invention is to provide a semiconductor device having a pluglike contact capable of suppressing excess reaction on a Ti/polysilicon interface and stably lowering contact resistance.
When forming the aforementioned pluglike contact 9, it is possible to simultaneously form a pluglike local wire 24 shown in FIGS. 22A and 22B. The term xe2x80x9cpluglike local wirexe2x80x9d indicates a local wire consisting of a conductor filling up a groove communicating with an upper connected portion and a lower connected portion. Provision of the pluglike local wire is effective in a portion such as a DRAM array part having no allowance in a space for laying out a general local wire. In general, however, the pluglike local wire of polysilicon disadvantageously has a higher resistance value than the general local wire.
Accordingly, another object of the present invention is to provide a semiconductor device capable of stably lowering the resistance value of a pluglike local wire.
In each of a peripheral circuit part and a logic circuit part of a DRAM, a contact 27 and a CoSi2 film 11 is formed on a source/drain region 2 of a transistor as shown in FIG. 20A, for forming a low-resistance contact. However, the CoSi2 film 11 may be heterogeneously formed on the source/drain region 2 due to a factor such as heat treatment. In this case, junction leakage is disadvantageously increased.
Further, CoSi2 may abnormally diffuse under an LDD (lightly doped drain) spacer 6 bounding on the transistor. In this case, the transistor characteristics are disadvantageously deteriorated.
Accordingly, still another object of the present invention is to provide a semiconductor device comprising a pluglike local wire, yet having a low resistance value.
A gate electrode contact 28 shown in FIGS. 21A and 21B is formed with no CoSi2 film 11 shown in FIG. 20A but a bit line 14 is directly in contact with a gate electrode 4 only through a barrier metal film 13, in order to avoid a complicated process. Thus, the gate electrode contact 28 disadvantageously has relatively high contact resistance.
Accordingly, a further object of the present invention is to provide a semiconductor device capable of stably implementing low resistance in a gate electrode contact.
In order to attain the aforementioned objects, a semiconductor device according to the present invention comprises an upper connected portion, which is an upper conductor portion, having a lower surface covered with a barrier metal film, a lower connected portion which is a lower conductor portion and a connecting portion for electrically connecting the barrier metal film and the lower connected portion with each other, and a layer essentially consisting of silicide having resistivity of not more than 100 xcexcxcexa9xc2x7cm is provided between the connecting portion and the barrier metal film to cover the upper surface of the connecting portion.
The connecting portion and the barrier metal film are not directly in contact with each other due to the aforementioned structure. Thus, the connecting portion does not react with the barrier metal film also when the same is made of polysilicon or the like, while the silicide layer has a low resistance value and hence contact resistance can be stably lowered.
Preferably, the connecting portion includes a conductor embedded in a hole communicating with the upper connected portion and the lower connected portion. Also when the connecting portion is formed by the so-called pluglike contact, the contact resistance can be stably lowered due to this structure.
Preferably, the upper connected portion includes a bit line contact. The contact resistance between the bit line contact and a pluglike contact in a memory cell can be stably lowered due to this structure.
Preferably, the upper connected portion includes a capacitor contact. The contact resistance between the capacitor contact and the pluglike contact in the memory cell can be stably lowered due to this structure.
Preferably, the lower end of the connecting portion is directly connected to a source or drain region provided on a semiconductor substrate without through a silicide film. It is possible to prevent junction leakage to the source/drain region caused when the silicide film is homogeneous, due to this structure.
Preferably, the lower end of the connecting portion is directly connected to a gate electrode. Excess reaction between the gate electrode and the barrier metal film can be prevented due to this structure.
Preferably, the connecting portion is a local wire formed by a conductor filing up a groove communicating with the upper connected portion and the lower connected portion. In a semiconductor device comprising the so-called pluglike local wire, the pluglike local wire does not react with the barrier metal film also when the same is made of polysilicon or the like, while the silicide layer has a low resistance value and hence the contact resistance can be stably lowered due to this structure.
Preferably, the silicide is any material selected from a group consisting of CoSi2, TiSi2, NiSi2, PdSi, ZrSi, HfSi, PtSi, CuSi, AuSi and AgSi. A layer of silicide having low resistivity can be formed for stably lowering the contact resistance due to this structure.
A method of manufacturing a semiconductor device according to the present invention comprises a metal film forming step of forming a metal film on the upper surface of a connecting portion containing polysilicon electrically connected to a lower connected portion for electrically connecting the lower connected portion with an upper connected portion, a silicification step of heat-treating the metal film and the connecting portion for causing silicification between the metal film and the connecting portion thereby forming a silicide film, a metal film removing step of removing a part of the metal film not silicified in the silicification step, an interlayer isolation film forming step of forming an interlayer isolation film to cover the silicide film, a perforation step of providing a vertical hole communicating with the silicide film in the interlayer isolation film and a wire forming step of forming a wire portion including a conductor in the vertical hole and on the interlayer isolation film.
The connecting portion and a barrier metal film are in contact with each other not directly but through the silicide film due to the aforementioned structure. Thus, the connecting portion does not react with the barrier metal film while the silicide layer has a low resistance value and hence a semiconductor device stably exhibiting low contact resistance can be manufactured.
Preferably, the silicide film consists of any material selected from a group consisting of CoSi2, TiSi2, NiSi2, PdSi, ZrSi, HfSi, PtSi, CuSi, AuSi and AgSi. A silicide layer having low resistivity can be formed for stably lowering the contact resistance due to this structure.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.